Frequency flip-flop



June 29, 1965 w. N. CARROLL FREQUENCY FLIP-FLOP Original Filed Deo. 26, 1957 4 Sheets-Sheet l w. N. CARROLL 3,192,484

FREQUENCY FLIP-FLOP 4 Sheets-Sheet 2 June Z9, 1965 Original Filed Dec. 26, 1957 omo June 29, lezsv W. N. CARROLL FREQUENCY FLIP-FLOP "osiginal Filed Dec. 26, 195'? 4 Sheets-Sheet 5 June 29, 1965 w. N. CARROLL 3,192,484

FREQUENCY FLIP-FLOP 'original Filed Dec. 2, 1957 A 4 sheets-sheet 4 |95 .imhy 205 .Z |80K /MK 9i 1.5mhy

OUT

United States Patent O 3,192,434 FREQUENCY FLIP-FLO?? William N. Carton, Rhinebeclr, NX., assigner to international Business Machines Corporation, New York, NX., a corporation of New York Continuation of appiicatiou Ser. No. 7%',299, Dec. 26,

i957. This application Aug. i7, 1959, Ser. No. 835,332 Ciaims. (Ci. 325i-39) The present invention relates to a circuit utilizing semiconductive ldevices. and more particularly to .a bistable circuit wherein the stable states of the device are identified by the frequency of the output signals. This is a continuation of my abandoned application, Serial No. 705,290, filed December 26, i957.

In circuits utilized with high speed computers, it is frequently desirable to combine or compare the effects of two or more separate signals in such a way that the identifiable characteristics of the resultant signal identify the relationship of the several signals. In the description of the invention herein given by way of disclosure, the principles of the invention are illustrated in a switching circuit or Hip-dop having two stable states and adapted to switch from one -state to the other upon application of a signal or signals of selected characteristics.

Circuits of this general class usually operate on D.C. level or pulse inputs and the resultant of the` logical function being provided is generally identified by the level of the output or outputs. Such circuit-s frequently utilize vacuum tubes or transistors to provide the desired logical operation. However, the inherent disadvantages of vacuum tubes such as relatively high operating voltage, characteristic fragility and short life, together with the poor signal to noise tolerance associated with such circuits imposes undesirable limiting conditions upon the nature and levels of the signals applied thereto. Whiie transistor circuits represented an improvement in certain of these limiting conditions, particularly low signal level, they retained the poor signal to noise characteristic and in addition were subject to many undesirable transient heating eects inherent in current ori-off transistor circuits.

To overcome such limitations of the prior art, the subject invention provides a new approach to logical design. Such logic, hereinafter defined `as frequency logic, basically employs frequency rather than DC. level to define a particular logical condition. While the principle of frequency logic is considered applicable to a variety of logical elements, the specific embodiment employed to illustrate the subject invention is a switching circuit or dip-flop whe-rein bistable circuit operation ,is controlled by selective application of two frequency signals to the input, and the state of the device is indicated by the frequency of the output signals. One embodiment of the invention is a two frequency switching circuit wherein seection between states is afforded by the `selective application of signals having the same frequencies as those of the output signals used to indicate the logical state of the device. in an alternate arrangement, four frequencies are utilized, two signals to provide yselection between states and four output signals to indicate the log-ical state of the device, two of the output signals having the same frequency as the input signals. Both embodiments utilize a local signal source, mixer circuits and selective filtering device-s to provide the logical function, and a feedback arrangement from one output to the input of the circuit to maintain the device in its stable state. Due to operation at a relatively constant energ level, the above described limitations of prior art logical devices are avoided and Iimproved voltage tolerance, improved signal tolerance, minimum transient heating effects and increased reliability are provided.

S@ Patented dune 2Q, 1.965

ice

Accordingly, a primary object -of the present invention is to provide an improved switching circuit.

Another object of the present invention is to provide a logical element adapted for use in y.a frequency logic system wherein logical conditions are specied by the frequency of the resultant signals. n

Still another object of the present invention is to provide a transistor switching circuit wherein the binary states of the circuit are identified by the frequency of the output signals.

A further object of the present invention is to provide a frequency flip-flop having two stable states wherein the state to which said tiipflop is set or maintained is selectively controlled by the frequency of the input signal.

Another object of the present invention is to provide an improve-d logical device wherein the logical condition to be provided determines the frequency of the input signal and the logical resultant is designated by the frequency of the output signals.

Still another object of the present invention is to provide a logical device utilizing the heterodyne principle.

Other objects of the invention will be pointed out in vthe following Vdescrip-tion and claims and illustrated in the accompanying drawings, which disclose, by way of example, the principle of the invention and the best mode, which has been contemplated, of applying that principle.

In the drawings:

FIG. 1 illustrates in simplified block form a first embodiment of the subject invention.

FG. 2 illustrates in simplified block form a second embodiment of the Isubject invention.

FIG. 3 illustrates in schematic form the subject invention illustrated in block form in FIG. 2.

FIG. 4 illustrates in schematic form an oscillator circuit shown as block in FIG. 2.

FIG. 5 illustrates in schematic form an inhibit circuit of the type shown las block 39 in FIG. 1.

Throughout the following description and in the accompanying drawings there are certain conventions employed which are familiar to certain of those skilled in the art. in the logical or block diagrams of the drawings, a conventional arrowhead indicates a circuit connection and the direct-ion of signal travel which is also the direction of control. In the description the general arrangement of several preferred embodimenas of this invention will be described with respect to the manner in which the various circuit components and apparatus .are interconnected as well as the general over-all `operation which is performed by those components vand apparatus. The description of the general arrangement will be followed by sepanate and detailed descriptions of a preferred embodiment of the invention and the various components and apparatus which so require it.

Referring now to the drawings and more particularly to FIG. 1 thereof, there is illust-rated in block form an embodiment of the subject invention utilizing a dual frequency input, the individual signals being hereinafter designated as f1 and f2, and a local signal source having a frequency hereinafter designated fo, wherein the frequency of f2 is equal to that of f1 -l-fo and wherein f1 f. Signal sources fo, f1, and f2 are shown in FIG. 1 as blocks 21, 23, and 25 respectively, wherein signal fo is provided by a local oscillator. While individual `signal sources are shown for signals f1 and f2 in the preferred embodiment, such signals would be available in a frequency logic system herein contemplated, and separate signal sources would not be required for each logical element. In the ensuing description, signals f1 and f2 will be designated as the binary l .and the binary O inputs to the illustrated embodiment, hereinater designated asia frequency tiip-op.

To set the iiip-flop .in the 1 state, signal f1 is applied momentarily through switch 27 and conductor 29 to mixer circuit 31, the second input to which is signal fo. After the signal f1 has been applied, the ,switch 2.7 is returned to the position as shown in FIG. l. Mixer circuit 31 operates as a conventional mixer to produce four signals on voutput conductor 33, the component signals fr and fo, the sum and difference signals fl-l-fu or f2 and fl-fn respectively. These signals are 4then applied to filter 35, a band-pass filter designed to pass a frequency range between and including f1 and f2. The resultant signals f1 and f2 are then applied through conductor 37 to inhibit circuit 39. Inhibit circuit 39, as more fully described hereinafter, is a circuit which cancels any signal which appears simultaneously on input conductor 37 and 29a, while passing any other signal applied to input conductor 37. As Ishown in FG. 1, the signal applied through conductor Z9 to mixer circuit 31, in the present example f1, is also applied through conductor 29a to inhibit circuit 39. Since signal f1 appears on both input conductors, it is cancelled and the resultant output signal on conductor 45, f2 designates one of the binary outputs of the frequency iiip-iiop. Thus the signal f1 applied to mixer 31 result-s in signal f2 being applied to output terminal 45.

Signal f2 on conductor 43 is also applied to mixer circuit 47, whe-re it is mixed with the signal ,to from oscillator 21. The resultant four output signals on conductor 49 are fo, f2, )C2-fo or f1 and z-t-f. Band pass filter 51, which is substantially identical to band pass filter 35, passes signal f2 and f1 through conductor 53 to inhibit circuit 55 which is identical with inhibit circuit 39.

It will be noted from the drawing that the input signal to mixer circuit 47 in the instant example, f2, is also applied through conductor 43a to inhibit circuit 55. The f2 signal is cancelled, and the remaining signal f1 is applied through conductor 57 to the second output terminal 59, which designates the other binary output from the flip-flop. The f1 signal is also applied through con-y ductor 57 and switches 26 and 27 as a feedback signal to the input of mixer 31 to thereby maintain the frequency flip-flop in its stable state.

VFrom the above description it will be recognized the signal f1, which is initially applied through switch 27 to mixer 31, is applied `as a feedback signal from inhibit circuit 55 upon closing switch 27. Thus the flip-ilop is set and maintained in the 1 `state by signal f1, and is identitied by signals f2 Yand f1 on output terminals 4S and 59 respectively.

To reset the frequency flip-liop to the state, switch 26 is operated, thereby simultaneously removing the feedback f1 signal to mixer circuit 31 and substituting the f2 signal. When mixed with the rfl, frequency from oscillator 21, the resultant output signals from mixer 31 on conductor 33, fo, f2, f2-f0 or f1 and f2|f0 are liltered by band-pass filter whereby the resultant signals f1 and f2 are applied through conductor 37 to inhibit circuit 39. However, since f2 is also applied through conductor 29a to inhibit circuit 39, it is cancelled within the inhibit circuit Iand the ersulting signal f1 is applied through conductor 43 to output terminal 45. Thus Signal f2 applied to the mixer circuit 31 causes signal f1 to appear on terminal 4S. Signal f1 is also appl-led through conductor 43 to mixer circuit 47 where it is mixed with fo, to provide the four output signals f1, fo, fl-l-fo or f2 and f1-f0. After filtering by band pass lilter 51, signals f1 and f2 are applied through conductor 53 to inhibit circuit 55, where the f1 signal applied as the second input to inhibit circuit 5S through conductor 43a is cancelled. The resulting signal f2 is then applied through conductor 57 to output terminal 59 and -reapplied as a feedback signal through switches 26 and 27 to mixer 31 to maintain the circuit in its second stable state. Thus the 0 state of the frequency flip-flop is identified by signals f1 and f2 on output terminals 45 and 59 respectively.

From the above description it will be recognized that for an input signal f1, output signals of f2 and f1 are provided on output terminals 45 and 59; for an input sign-al f2, output signals f1 and f2 are provided on output terminals i5 and 59 respectively. Since the frequency of f2 is equal to fl-I-fo, in a logical system as contemplated in the subject invention, signal source f2 might be provided from another logical device or common signal frequency source rather than requiring a separate signal source. A single frequency signal source could be utilized in the above described embodiment by selectively applying it to the mixer circuits in accordance with the logical function to 'be provided. Applying signal f1 to mixer 47, for example, would provide the same result as applying signal f2 to mixer 31, and vice versa. Using a single input signal source, the state to which the binary flip-tiop would be set would be controlled by the particular input and mixer to which the single frequency would be applied. Switches 26 and 27 might be any conventional electronic switch or selection matrix which would be operated long enough to initiate transition and then returned to its normally closed position.

While the input and output signals of the `above described embodiment utilize the same pair of frequencies, another embodiment of the subject invention shown in FIG. 2 utilizes a dual frequency input to obtain dual output signals of different frequencies, or a total of four different frequency signals, thereby eliminating the necessity of an inhibiting circuit. In the ensuing description, the input frequencies are 4designated as f1 and f2, while the corresponding output signals are designated as f1, f2, f3, f4 and the local oscillator is designated fo, wherein o f1 and f2, fa=fof1 and f4=fof2 SSUHIS 1 3nd f2 will be assumed to set and reset the iiip-iiop respectively` To `set the dip-flop to the 1 state, signal f1 is applied from signal generator 23 through switch 27 and conductor 61 to mixer 63, where it is mixed with the fo signal applied from oscillator 65 through conductor 67 to generate four output signals on conductor 69, fo, f1, fo-f-fl and fo-fl or f3. These signals onconductor 69 are applied to iilter networks 71 and 73, which are designed to pass signals of f3 and f4 frequencies respectively. Since signal fa is included in the outputs from mixer 63, it is applied through filter 71 and conductors 7d and to output terminal 7'7 las well as to the input of mixer circuit 79, where it is mixed with the fo signal on conductor S1 to generate a second series of output signals on conductor 33, fo, f3, )CV-f3 or f1 and f0-I-f3. These signals are in turn applied to filter networks and 37, which are designed to pass signals f1 and f2 respectively. In the example herein described, signal f1 is passed by lilter 85 to conductor 89 and applied through conductor 61 to output terminal 91 and as a feedback signal to the input of mixer 63 to maintain the circuit in the above described state.

To reset the flipliop to the zero state, switch 26 is operated, thereby simultaneously removing the f1 feedback signal and applying signal f2 from signal generator 25 through conductor 61 to mixer circuit 63 wherein it is mixed with signal fo from oscillator 65 to produce output signals fo, f2, fyi-f2, and f0-f2 or f4. These signals are applied through conductor 69 to filter networks 71 and 73, the latter of which is tuned to a frequency of f4, and the resultant f4 signal is applied through conductors 74 and 74a to output terminal 77 and to mixer circuit 7 9, where it is mixed with the fo signal from oscillator 65. The resultant output signals on conductor 83, fo, f4, )iV-f4 or f2 and ffl-., are applied to filter networks 85 and S7, the latter of which is tuned to a frequency of f2. The resultant output signal f2 is then applied through conductor 61 to output terminal 91 and reapplied as a feedback signal through conductor 61 to the input of mixer circuit 63 to maintain the flip-flop in the above described 0" state.

summarizing the operation of the above described emr areas-sa bodiment, when signal f1 is applied as the input signal to the frequency iiip-ilop, signals f3 and f1 are generated on output terminals 77 and 91; when signal f2 is applied as the input signal, output signals f4 and f2 are generated on output terminals 77 and 91 respectively. The above described arrangement of PEG. 2 utilizes the heterodyne principle of beating two signals and selective lters the resultant beat frequency signal as the output.

Referring now to FlG. 3 there is illustrated in schematic form the preferred embodiment of the subject invention shown in block form in FlG. 2. To set the flip-flop to the l state, the signal f1 is applied through conductor 61 and capacitor 99 to the base 161 of transistor 163, while the signal fo is applied from oscillator 65, shown in block form, through conductor 67 and capacitor 105 to the emitter 107 of transistor 1153. Transistor 153 and associated circuitry comprises the mixing stage shown as block 63 in FIG. 2, wherein signals applied to the base and emitter are mixed to the four frequencies heretofore designated, f1, fg, fO-i-fl and fo-fl or f3 on collector 169. The resultant signals are in turn applied through conductor 69 to filter networks 71 and 73. 1n the preferred embodiment, filter networks 71 and 73 comprise tuned circuits which are tuned to resonant frequencies f3 and f4 respectively. Parallel resonant circuit 71 comprises transformer windings 111 and 113 and associated capacitors 115 and 117, while parallel resonant circuit 73 comprises transformer windings 119 and 121 and associated capacitors 125 and 125 respectively. In the instant example, the resultant output signal from filter circuit 71 is adapted through conductor 75 to the base 127 of transistor 129. Transistor 12? and associated circuitry is a power amplifier circuit which functions as a level setter to raise the level or" the output signal of filter circuit 71 to the level required for mixer stage '79. Since the amplifier circuit performs no logical function, it was omitted from the logical diagram of FIG. 2. The collector 131 of transistor 129 is connected to a source of negative potential at terminal 133, while the emitter 135 is connected through potentiometer 137 to a source of positive potential at terminal 139.

i The signal generated by emitter current iiow through potentiometer 137 is applied through variable arm 141 and conductor 74a to base 143 of transistor 145, which functions as mixer circuit 79, while the signal from oscillator 65 is applied through conductor 51 and capacitor 1417 to the emitter 149 of transistor 145. The resultant output signals on collector 151, fo, f3, ,fo-f3, or f1 and O-l-g are applied through conductor $3 to filter circuits 85 and 87. Filter circuit 85, comprising transformer windings 153, 155 and associated capacitors 157, 159 respectively is a resonant circuit tuned to frequency f1; filter network 87 comprising transformer windings 151, 163 and associated capacitors 165, 167 respectively is a resonant circuit tuned to frequency f2. The resultant signal from filter circuit 25 is applied through conductor S9 to base 169 of transistor 171, which functions as a power amplifier providing the same impedance matching and isolation functions as power amplifier 129. The resultant signal from emitter 175 of transistor 171 is applied to output terminal 91, and the signal developed across potentiometer 173, which provides a gain adjustment to compensate for the variation in transformer characteristics, is then coupled through conductor 61 and capacitor 99 to the base 151 of mixer 53 as a feedback signal to provide the required regenerative flip-hop action. The two output terminals 77 and 91 under the above described conditions correspond to those shown in FIG. 2.

To reset the subject device to the 0 state, a signal of frequency f2 is applied from signal generator 25 through switch 25, conductor 51 and capacitor 99 to the base 191 of transistor 103 where it is mixed with the signal fu from oscillator 65 applied to emitter 167 of transistor 103. One of the frequencies generated by the mixer circuit, f4, is applied through conductor to the base 127 of power amplifier 129. The resultant output signal from the emitter of the power amplier transistor is applied to output terminal 77, and through potentiometer 137 to the base 143 of transistor 145. The second input to the mixer circuit comprises the fo signal from oscillator 65 which is applied to the emitter 149 of transistor 145. Filter network 57 is tuned to one of the four output signals generated by. mixer 145, f4. The output from filter network 87 is applied through conductor to the base 169 of power amplifier 171. The output from emitter 175 of transistor 171 is in turn applied to output terminal 91 and a portion thereof is applied through potentiometer 173, conductor 51, switches 25 and 27 and capacitor 59 to the base 161 of transistor 163 to provide the required regenerative flip-flop action for the second stable state.

1n the above-described embodiment, the amplitude of the output signals is approximately 60 millivolts peak to peak. The amplitude of oscillator 65 is approximately 1.5 volts peak to peak and the output signals on terrninal 77 and 91 are approximately 2 volts peak to peak.

Exemplary values of the circuit components and frequencies employed for the above described frequency flip-flop are as follows:

Signal: KC f1 580 f2 680 f3 400 f., 300 fo 980 Filter 71:

Resonant frequency 400 kc. Transformer winding lll-1.54 mh. Transformer winding i12-1.59 mh. Capacitor 11S-110 auf. Capacitor 117-103 upf.

Filter 73:

Resonant frequency 300 kc. Transformer winding 119-496 ph. Transformer winding 121-496 ph. Capacitor 12S-496 auf. Capacitor 12S-496 auf.

Filter 35:

Resonant frequency 580 kc. Transformer winding 153-165 uh. Transformer winding 155-165 uh. Capacitor 157-490 wif. Capacitor 159-490 auf.

Filter 87:

Resonant frequency 680 kc. Transformer winding ll-1.5 mh. Transformer winding 16B-1.5 mh. Capacitor -37 auf. Capacitor 167-32 fuif.

Referring now to FIG. 4, there is illustrated in schematic form the oscillator circuit shown as blocl: 65 in F165. 2 and 3. ln the preferred embodiment constructed in accordance with the principles of the present invention, a transistorized Colpitts oscillator is utilized. Resistors 151 and 153 connect-ed to -3 volts and ground respectively provide DC. bias to the base 155 of transistor 137, while capacitor 139 effectively biases the base at A C. ground, thereby enabling the circuit to function in a grounded base configuration. Transformer primary winding 151 connected to emitter 153 of transistor 137 and secondary winding 155 connected through conductor to the collector 1915 of transistor 187 provides a feedback to the collector to sustain oscillation. Capacitors and 253 together with transformer winding are the frequency determining components of the oscillator.

The output from thc oscillator is applied through conductor 265 to base 267 of emitter follower 2b?, which functions as a buffer amplifier to prevent changes in the load from varying the oscillator frequency and power amplifies the oscillator output signal to the desired operating level.

Referring to FIG. 5, there is illustrated one arrangement of an inhibit circuit of the type shown as blocks 39 and 55 in FIG. l. Since the inhibit circuits are identical, inhibit circuit 35- will be described as illustrative, and the inputs thereto and outputs therefrom labeled accordingly.

As heretofore described, inhibit circuit 3% has two inputs, one from filter network 35 through conductor 37,

the second the input signal through conductor 22a. in the FIG. l arrangement, signals f1 and f2 re always applied from filter 35 through conductor 37 irrespective of the frequency of the input signal. As shown, the input signal is applied across transformer primary winding and capacitor 223 to ground. The circuit comprising secondary winding 225 and capacitor is tuned to frequency f1, while the circuit comprising secondary winding 229 and capacitor 231 is tuned to frequency f2. Irres ective of the frequency of the input signal, signal f1 will be applied through conductor 233 to base 235 of transistor 237, and signal f2 will be applied through conductor 239 to base 2st of transistor 2st-3. The second input to inhibit circuit 3f) will be the input signal, f1 in the assumed example which is applied through conductor 29a across transformer primary winding SiS-i and capacitor 253 to ground. The circuit comA rising secondary winding 255 and capacitor 257 is tuned to frequency fg, while the circuit comprising transformer secondary winding 259 and capacitor 261 is tuned to frequency f1. Diode 263 and capacitor 2%5 rectify signal f2 before it is applied through conductor 25'? to base 25S' of transistor 27E, while diode 273 and capacitor 275 rectify signal f1 before it is applied through conductor 27", to base 2@ of transistor 23l. lrnitters 283 and 235 of transistors 243 and 273i are connected through common resistor to ground, while emitters 289 and 291 of transistors 237 and 231 respectively are connected through common resister 293 to ground. Collectors 225 and 297 are connected through resistor 299 to a source of negative potential, and to common output conductor 43. Depending on whether f1 or f2 is the input signal, a necative potential will be applied to the base of transistors 281 or 271i to inhibit its associated transistor 23'? or 243 respectively. In the instant situation where the input signal is f1, transistor 28l is turned on and thereby inhibits transistor 237. Under this condition, transistor 271 remains o due to the absence of signal f2, and the signal applied to base of transistor 243 is amplified and applied through collector 29S to output conductor 43. On the other hand, if the input signal is f2, transistor 271 is turned on, thereby i-nhibiting transistor 241, and the f1 ignal is amplified by transistor 237 and applied through collector 227' to output conductor 243. lnhibit circuit 55 functions in the same identical manner to inhibit the signal applied to both inputs and pass the other input signal.

While the contemplated environment for the above described invention residcs in a frequency logic system, the circuit is not limited thereto, since the output signal could readily be rectified to operate in a conventional logic system. Within a frequency logic system, various logical devices could be employed using different frequencies to identify particular logical conditions and thereby utilize common conductors. Such devices could be separated where desired by appropriate filter networks.

While there .has been shown and described and pointed out the fundamental novel features of the invention as applied to a plurality of embodiments, it will be understood that various omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art, without departing from the spirit of the invention, lt is the intention, therefore, to be limited only as indicated by the scope of the following claims.

What is claimed is:

l. A bistable switching device having a plurality of outputs wherein the frequency of the output signals indicates the binary state of said device comprising, in combi-.ation, a dual frequency signal source, means for selectively applying an input signal from said dual frequency 'gnal source to said device, a signal source of constant frequency, means for heterodyning said input signal with constant frequency signal, means for filtering one of the resultant heterodyned signals and applying said filtered signal to one of said outputs, means for heterodyning said filtered signal and said constant frequency signal, means for filtering a second one of said resultant heterodyned signals and applying said second filtered signal to said second output, the frequency of said output signals identifying the stable state of said device, the frequency of said second output signal being equal to that of said input signal, and means for maintaining said device in said stable state by reapplying said second output signal to the input of said device.

2. A switching circuit having a plurality of stable states wherein the state of said circuit is controlled by the frequency of the input signal applied to the input of said device comprising, in combination, means for applying an input signal of predetermined frequency to said circuit, a fixed frequency signal source for generating a fixed frequency signal, means responsive to said input signal and said fixed frequency signal for generating a plurality of signals of different frequencies including a signal of frequency corresponding to a function of said input signal, means for detecting said corresponding signal, means responsive to said detected signal for generating a maintaining signal equal in frequency to the frequency of the input signal applied, and means feeding said maintaining signal back to said input for maintaining said switching circuit in t e same stable state to which it was switched by said input signal, upon discontinuance of said input signal.

3. A bistable switching circuit having a dual frequency signal source wherein the stable states of said circuit are identified by signals having frequencies corresponding to those of said dual frequency signal source comprising, in combination, means for selectively applying one of said dual frequency signals to the input of said circuit, a constant frequency signal source for generating a constant frequency signal, means for combining said applied signal and said constant frequency signals to provide a first plurality of signals including signal corresponding in frequency to those of said dual frequency source selected, means for detecting one of said plurality of signals, means for combining said detected signal with said constant frequency signal to provide a second plurality of signals including signals corresponding in frequency to said dual frequency signal source selected, means to detect a signal from said second plurality of signals, said last detected signal being equal in frequency to said applied signal from said dual frequency signal source, and means for applying said second detected signal to said input of said switching circuit to maintain said circuit in said stable state.

4i. A bistable switching circuit wherein the state of said device is controlled by the frequency of the signals applied to the input of said device comprising in combination means for applying an alternating input signal to the input of said circuit, a constant frequency signal source for generating a constant frequency signal, means responsive to said input signal and said constant frequency signal for generating a first plurality of signals including said input and constant frequency signals and combinations thereof, rneans for detecting one of said first plurality of signals, said detected signal having a frequency corresponding to a function of said input and fixed constant frequency signals, means responsive to said detected signal and said constant frequency signal for generating a second plurality of signals, means for detecting one of said second plurality of signals, said latter detected signal having a frequency equal to that of said input signal, Whereby said detected signals comprise the outgnut signals identifying the stable state of said device, and feedback means to apply said second detected signal to said input to maintain said switching circuit in said stable state.

5. In combination with means for generating a number of different function signals characterized by respective dilerent frequencies, a logical device having input means, means for selectively coupling said function-signal generating means to said input means, said logical device providing a number of dilerent frequency output signals equal to the number of said function signals and related, res ectively, to said different function signals; said logical device including means for generating a constant frequency signal and means for selectively heterodyning each said function signal with said constant frequency signal to provide, a unique output signal of distinct frequency characteristics including, at least, a frequency identical to that of the function signal, means for feeding back said unique output signal, to said input means and means for disconl@ nesting said function signal generating means whereby said unique output signal of a distinct frequency is maintained.

Reiterences Cited by theExaminer UNITED STATES PATENTS 2,388,566 10/45 Nyquist 178-66 2,406,932 9/46 Tuniek 3314-43 2,652,451 9/53 Peten 178-88 2,770,722 11/58 Arms 258-15 2,829,255 4/58 1301i@ 331-39 2,914,249 11/59 Goodall 23S-176 2,914,871 11/59 Deming@ 25o-15 2,928,088 3/60 Takahasi 308-88 2,934,658 4/50 Lewis 307-885 2,948,818 8/60 Goto 307-88 3,011,706 12/61 Goto 3213*-92 DAVID 3. GALVIN, Primary Examiner.

EVERETT R. REYNOLDS, IRVlNG L. SRAGOW,

Examiners. 

5. IN COMBINATION WITH MEANS FOR GENERATING A NUMBER OF DIFFERENT FUNCTION SIGNALS CHARACTERIZED BY RESPECTIVE DIFFERENT FREQUENCIES, A LOGICAL DEVICE HAVING INPUT MEANS, MEANS FOR SELECTIVELY COUPLING SAID FUNCTION-SIGNAL GENERATING MEANS TO SAID INPUT MEANS, SAID LOGICAL DEVICE PROVIDING A NUMBER OF DIFFERENT FREQUENCY OUTPUT SIGNALS EQUAL TO THE NUMBER OF SAID FUNCTION SIGNALS AND RELATED, RESPECTIVELY, TO SAID DIFFERENT FUNCTION SIGNALS; SAID LOGICAL DEVICE INCLUDING MEANS FOR GENERATING A CONSTANT FREQUENCY SIGNAL AND MEANS FOR SELECTIVELY HETERODYING EACH SAID FUNCTION SIGNAL WITH SAID CONSTANT FREQUENCY SIGNAL TO PROVIDE, A UNIQUE OUTPUT SIGNAL OF DISTINCT FREQUENCY CHARACTERISTICS INCLUDING, AT LEAST A FREQUENCY INDENTICAL TO THAT OF THE FUNCTION SIGNAL, MEANS FOR FEEDING BACK SAID UNIQUE OUTPUT SIGNAL, TO SAID INPUT MEANS AND MEANS FOR DISCONNECTING SAID FUNCTION SIGNAL GENERATING MEANS WHEREBY SAID UNIQUE OUTPUT OF A DISTINCT FREQUENCY IN MAI 